; Generated by gcc 2.95.2 19991024 (release) for ARM/RISC OS
__r0	RN	0
__a1	RN	0
__a2	RN	1
__a3	RN	2
__a4	RN	3
__v1	RN	4
__v2	RN	5
__v3	RN	6
__v4	RN	7
__v5	RN	8
__v6	RN	9
__sl	RN	10
__fp	RN	11
__ip	RN	12
__sp	RN	13
__lr	RN	14
__pc	RN	15
__f0	FN	0
__f1	FN	1
__f2	FN	2
__f3	FN	3
__f4	FN	4
__f5	FN	5
__f6	FN	6
__f7	FN	7
	AREA |C$$code1|, CODE, READONLY
|gcc2_compiled.|
	ALIGN
|subdv_table|
	KEEP |subdv_table|
	DCD	0
	DCD	0
	DCD	0
	DCD	0
	DCD	0
	DCD	0
	DCD	0
	DCD	0
	DCD	0
	DCD	0
	DCD	0
	DCD	1
	DCD	1
	DCD	1
	DCD	1
	DCD	1
	DCD	1
	DCD	2
	DCD	2
	DCD	2
	DCD	2
	DCD	3
	DCD	2
	DCD	3
	DCD	3
	DCD	4
	DCD	3
	DCD	4
	DCD	3
	DCD	4
	DCD	4
	DCD	5
	DCD	4
	DCD	5
	DCD	4
	DCD	6
	DCD	5
	DCD	6
	DCD	5
	DCD	6
	DCD	5
	DCD	7
	DCD	6
	DCD	7
	DCD	6
	DCD	7
	ALIGN
|huf_tbl_noESC.18|
	KEEP |huf_tbl_noESC.18|
	DCD	1
	DCD	2
	DCD	5
	DCD	7
	DCD	7
	DCD	10
	DCD	10
	DCD	13
	DCD	13
	DCD	13
	DCD	13
	DCD	13
	DCD	13
	DCD	13
	DCD	13
	ALIGN
|choose_table_nonMMX|
	KEEP |choose_table_nonMMX|
	; args = 0, pretend = 0, frame = 16, alloca = 0
	; frame_needed = 0, anonymous_args = 0
	; nonlocal_label = 0, nonlocal_goto = 0
	stmfd	__sp!, {__v1, __v2, __v3, __v4, __v5, __v6, __lr}
	sub	__sp, __sp, #16
	mov	__v4, __a2
	mov	__a2, __a1
	mov	__lr, __a2
	mov	__a1, #0
	mov	__a4, __a1
	str	__a3, [__sp, #0]
|L..42|
	ldr	__a3, [__lr], #4
	ldr	__ip, [__lr], #4
	cmp	__a1, __a3
	movlt	__a1, __a3
	cmp	__a4, __ip
	movlt	__a4, __ip
	cmp	__lr, __v4
	bcc	|L..42|
	cmp	__a1, __a4
	movge	__lr, __a1
	movlt	__lr, __a4
	cmp	__lr, #15
	ldrls	__pc, [__pc, __lr, asl #2]
	b	|L..86|
	ALIGN
	ALIGN
|L..110|
	DCD	|L..50|
	DCD	|L..51|
	DCD	|L..58|
	DCD	|L..58|
	DCD	|L..78|
	DCD	|L..78|
	DCD	|L..78|
	DCD	|L..78|
	DCD	|L..78|
	DCD	|L..78|
	DCD	|L..78|
	DCD	|L..78|
	DCD	|L..78|
	DCD	|L..78|
	DCD	|L..78|
	DCD	|L..78|
|L..50|
	mov	__a1, __lr
	b	|L..111|
|L..51|
	ldr	__a3, [__sp, #0]
	ldr	__ip, |L..114|
	ldr	__a3, [__a3, #0]
	mov	__a1, __a2
	str	__a3, [__sp, #12]
	mov	__a2, #0
	ldr	__lr, [__ip, #28]
|L..53|
	ldr	__ip, [__a1, #0]
	ldr	__a3, [__a1, #4]
	add	__a1, __a1, #8
	add	__a3, __a3, __ip, asl #1
	ldrb	__a4, [__lr, __a3]	; zero_extendqisi2
	cmp	__a1, __v4
	add	__a2, __a2, __a4
	bcc	|L..53|
	ldr	__a4, [__sp, #12]
	mov	__a1, #1
	ldr	__a3, [__sp, #0]
	add	__ip, __a4, __a2
	str	__ip, [__a3, #0]
	b	|L..111|
|L..58|
	ldr	__v3, |L..114|+4
	ldr	__a4, [__sp, #0]
	ldr	__a3, |L..114|+8
	ldr	__a4, [__a4, #0]
	str	__a4, [__sp, #12]
	sub	__ip, __lr, #1
	ldr	__v5, [__a3, __ip, asl #2]
	mov	__a1, __a2
	ldr	__a3, |L..114|+12
	mov	__lr, #0
	ldr	__ip, |L..114|
	mov	__v1, __v5
	cmp	__v1, #2
	moveq	__v3, __a3
	ldr	__v2, [__ip, __v1, asl #4]
|L..62|
	ldmia	__a1, {__a2, __a3}	; phole ldm
	add	__a1, __a1, #8
	mla	__ip, __v2, __a2, __a3
	ldr	__a4, [__v3, __ip, asl #2]
	cmp	__a1, __v4
	add	__lr, __lr, __a4
	bcc	|L..62|
	mov	__ip, __lr, asl #16
	mov	__ip, __ip, lsr #16
	mov	__lr, __lr, lsr #16
	cmp	__lr, __ip
	movhi	__lr, __ip
	addhi	__v1, __v5, #1
|L..65|
	ldr	__a3, [__sp, #12]
	mov	__a1, __v1
	ldr	__a4, [__sp, #0]
	add	__ip, __a3, __lr
	b	|L..112|
|L..78|
	ldr	__ip, [__sp, #0]
	ldr	__a3, |L..114|+8
	ldr	__ip, [__ip, #0]
	mov	__a1, __a2
	str	__ip, [__sp, #12]
	sub	__ip, __lr, #1
	ldr	__lr, [__a3, __ip, asl #2]
	mov	__v1, #0
	ldr	__a4, |L..114|
	mov	__a3, __lr, asl #4
	ldr	__ip, [__a4, __a3]
	mov	__v2, __v1
	str	__ip, [__sp, #4]
	add	__a4, __a4, #12
	ldr	__a3, [__a4, __a3]
	mov	__v3, __v1
	str	__a3, [__sp, #8]
	add	__ip, __lr, #1
	ldr	__v6, [__a4, __ip, asl #4]
	add	__a3, __lr, #2
	ldr	__v5, [__a4, __a3, asl #4]
|L..80|
	ldr	__a4, [__a1, #0]
	ldr	__a3, [__a1, #4]
	ldr	__ip, [__sp, #4]
	mla	__ip, __a4, __ip, __a3
	ldr	__a3, [__sp, #8]
	add	__a1, __a1, #8
	ldrb	__a4, [__v6, __ip]	; zero_extendqisi2
	cmp	__a1, __v4
	ldrb	__a2, [__a3, __ip]	; zero_extendqisi2
	add	__v2, __v2, __a4
	ldrb	__a3, [__v5, __ip]	; zero_extendqisi2
	add	__v1, __v1, __a2
	add	__v3, __v3, __a3
	bcc	|L..80|
	mov	__a1, __lr
	cmp	__v1, __v2
	movgt	__v1, __v2
	addgt	__a1, __a1, #1
|L..83|
	cmp	__v1, __v3
	movgt	__v1, __v3
	addgt	__a1, __lr, #2
|L..84|
	ldr	__a4, [__sp, #12]
	ldr	__a3, [__sp, #0]
	add	__ip, __a4, __v1
	str	__ip, [__a3, #0]
	b	|L..111|
|L..86|
	ldr	__ip, |L..114|+16
	cmp	__lr, __ip
	ble	|L..87|
	ldr	__ip, |L..114|+20
	ldr	__a4, [__sp, #0]
	mvn	__a1, #0
	b	|L..112|
|L..87|
	ldr	__a3, |L..114|
	ldr	__a4, [__sp, #0]
	sub	__lr, __lr, #15
	ldr	__ip, [__a3, #388]
	mov	__v1, #24
	ldr	__a4, [__a4, #0]
	cmp	__ip, __lr
	str	__a4, [__sp, #12]
	mov	__a4, __a3
	bge	|L..89|
	add	__a3, __a4, #4
|L..90|
	add	__v1, __v1, #1
	cmp	__v1, #31
	bgt	|L..89|
	ldr	__ip, [__a3, __v1, asl #4]
	cmp	__ip, __lr
	blt	|L..90|
|L..89|
	sub	__a1, __v1, #8
	cmp	__a1, #23
	mov	__v3, __v1, asl #4
	bgt	|L..95|
	add	__a3, __a4, #4
	b	|L..113|
|L..115|
	ALIGN
|L..114|
	DCD	|ht|
	DCD	|table56|
	DCD	|huf_tbl_noESC.18|
	DCD	|table23|
	DCD	8206
	DCD	100000
|L..96|
	add	__a1, __a1, #1
	cmp	__a1, #23
	bgt	|L..95|
|L..113|
	ldr	__ip, [__a3, __a1, asl #4]
	cmp	__ip, __lr
	blt	|L..96|
|L..95|
	mov	__v2, __a1
	ldr	__a3, [__a4, __v2, asl #4]
	mov	__a1, __a2
	ldr	__ip, [__a4, __v3]
	mov	__a4, #0
	ldr	__a2, |L..117|
	add	__a3, __ip, __a3, asl #16
|L..101|
	ldr	__ip, [__a1], #4
	cmp	__ip, #0
	ldr	__lr, [__a1], #4
	beq	|L..102|
	cmp	__ip, #14
	movgt	__ip, #15
	addgt	__a4, __a4, __a3
|L..103|
	mov	__ip, __ip, asl #4
|L..102|
	cmp	__lr, #0
	beq	|L..104|
	cmp	__lr, #14
	movgt	__lr, #15
	addgt	__a4, __a4, __a3
|L..105|
	add	__ip, __ip, __lr
|L..104|
	ldr	__ip, [__a2, __ip, asl #2]
	cmp	__a1, __v4
	add	__a4, __a4, __ip
	bcc	|L..101|
	mov	__ip, __a4, asl #16
	mov	__ip, __ip, lsr #16
	mov	__a4, __a4, asr #16
	cmp	__a4, __ip
	movgt	__a4, __ip
	movgt	__v2, __v1
|L..108|
	ldr	__a3, [__sp, #12]
	add	__ip, __a3, __a4
	ldr	__a4, [__sp, #0]
	mov	__a1, __v2
|L..112|
	str	__ip, [__a4, #0]
|L..111|
	b	|L..116|
|L..118|
	ALIGN
|L..117|
	DCD	|largetbl|
|L..116|
	add	__sp, __sp, #16
	ldmfd	__sp!, {__v1, __v2, __v3, __v4, __v5, __v6, __pc}
	ALIGN
	EXPORT	|count_bits_long|
|count_bits_long|
	; args = 0, pretend = 0, frame = 4, alloca = 0
	; frame_needed = 1, anonymous_args = 0
	; nonlocal_label = 0, nonlocal_goto = 0
	mov	__ip, __sp
	stmfd	__sp!, {__v1, __v2, __v3, __v4, __v5, __v6, __fp, __ip, __lr, __pc}
	sub	__fp, __ip, #4
	cmp	__sp, __sl
	bllt	|__rt_stkovf_split_small|
	sub	__sp, __sp, #4
	mov	__v2, #576
	mov	__v5, __a2
	add	__ip, __v5, #252
	add	__ip, __ip, #2048
	ldmda	__ip, {__a4, __ip}
	orr	__a4, __ip, __a4
	mov	__ip, #0
	mov	__v6, __a1
	mov	__v4, __a3
	str	__ip, [__sp, #0]
	cmp	__a4, __ip
	bne	|L..121|
	mvn	__a1, #3
	mvn	__a2, #7
|L..122|
	sub	__v2, __v2, #2
	cmp	__v2, #1
	ble	|L..121|
	add	__ip, __v5, __v2, asl #2
	ldr	__a4, [__ip, __a1]
	ldr	__a3, [__ip, __a2]
	orrs	__a4, __a4, __a3
	beq	|L..122|
|L..121|
	mov	__v1, #0
	mov	__v3, __v1
	cmp	__v2, #3
	str	__v2, [__v4, #8]
	ble	|L..127|
	mvn	__lr, #7
|L..129|
	add	__a3, __v5, __v2, asl #2
	ldr	__a1, [__a3, #-4]
	ldr	__a2, [__a3, __lr]
	ldr	__a4, [__a3, #-12]
	ldr	__a3, [__a3, #-16]
	orr	__ip, __a1, __a2
	orr	__ip, __ip, __a4
	orr	__ip, __ip, __a3
	cmp	__ip, #1
	bhi	|L..127|
	add	__ip, __a4, __a3, asl #1
	add	__ip, __a2, __ip, asl #1
	ldr	__a3, |L..144|
	add	__ip, __a1, __ip, asl #1
	ldrb	__a2, [__a3, __ip]	; zero_extendqisi2
	sub	__v2, __v2, #4
	ldr	__a3, |L..144|+4
	cmp	__v2, #3
	ldrb	__a4, [__a3, __ip]	; zero_extendqisi2
	add	__v1, __v1, __a2
	add	__v3, __v3, __a4
	bgt	|L..129|
|L..127|
	cmp	__v1, __v3
	str	__v1, [__sp, #0]
	mov	__ip, #0
	str	__ip, [__v4, #72]
	ble	|L..132|
	str	__v3, [__sp, #0]
	add	__ip, __ip, #1
	str	__ip, [__v4, #72]
|L..132|
	str	__v2, [__v4, #4]
	ldr	__a1, [__sp, #0]
	cmp	__v2, #0
	str	__a1, [__v4, #88]
	beq	|L..143|
	ldr	__ip, [__v4, #24]
	cmp	__ip, #2
	bne	|L..134|
	ldr	__a3, |L..144|+8
	ldr	__ip, [__v6, __a3]
	mov	__v3, __v2
	add	__v1, __ip, __ip, asl #1
	cmp	__v1, __v2
	movge	__v1, __v2
	b	|L..136|
|L..134|
	cmp	__ip, #0
	bne	|L..137|
	add	__a4, __v6, #32512
	add	__a4, __a4, #156
	add	__a2, __v6, #66560
	sub	__ip, __v2, #2
	ldrb	__a1, [__a4, __ip]	; zero_extendqisi2
	add	__a2, __a2, #536
	str	__a1, [__v4, #56]
	sub	__a3, __v2, #1
	ldrb	__ip, [__a4, __a3]	; zero_extendqisi2
	mov	__v1, __a1
	str	__ip, [__v4, #60]
	add	__ip, __v1, __ip
	add	__ip, __ip, #2
	ldr	__v3, [__a2, __ip, asl #2]
	add	__a3, __v1, #1
	ldr	__v1, [__a2, __a3, asl #2]
	cmp	__v3, __v2
	bge	|L..136|
	add	__a1, __v5, __v3, asl #2
	add	__a2, __v5, __v2, asl #2
	ldr	__ip, |L..144|+12
	mov	__a3, __sp
	mov	__lr, __pc
	ldr	__pc, [__v6, __ip]
	str	__a1, [__v4, #40]
	b	|L..136|
|L..137|
	mov	__ip, #7
	str	__ip, [__v4, #56]
	ldr	__a3, |L..144|+16
	mov	__v3, __v2
	ldr	__v1, [__v6, __a3]
	add	__ip, __ip, #6
	str	__ip, [__v4, #60]
	cmp	__v1, __v3
	movge	__v1, __v3
|L..136|
	cmp	__v2, __v1
	movlt	__v1, __v2
	cmp	__v2, __v3
	movge	__v2, __v3
	cmp	__v1, #0
	ble	|L..141|
	mov	__a1, __v5
	add	__a2, __v5, __v1, asl #2
	ldr	__ip, |L..144|+12
	mov	__a3, __sp
	mov	__lr, __pc
	ldr	__pc, [__v6, __ip]
	str	__a1, [__v4, #32]
|L..141|
	cmp	__v1, __v2
	bge	|L..142|
	add	__a1, __v5, __v1, asl #2
	add	__a2, __v5, __v2, asl #2
	ldr	__ip, |L..144|+12
	mov	__a3, __sp
	mov	__lr, __pc
	ldr	__pc, [__v6, __ip]
	str	__a1, [__v4, #36]
|L..142|
	ldr	__a1, [__sp, #0]
|L..143|
	ldmea	__fp, {__v1, __v2, __v3, __v4, __v5, __v6, __fp, __sp, __pc}
|L..145|
	ALIGN
|L..144|
	DCD	|t32l|
	DCD	|t33l|
	DCD	67200
	DCD	227008
	DCD	67128
	ALIGN
	EXPORT	|best_huffman_divide|
|best_huffman_divide|
	; args = 4, pretend = 0, frame = 812, alloca = 0
	; frame_needed = 1, anonymous_args = 0
	; nonlocal_label = 0, nonlocal_goto = 0
	mov	__ip, __sp
	stmfd	__sp!, {__v1, __v2, __v3, __v4, __v5, __v6, __fp, __ip, __lr, __pc}
	sub	__fp, __ip, #4
	sub	__ip, __sp, #812
	cmp	__ip, __sl
	bllt	|__rt_stkovf_split_big|
	sub	__sp, __sp, #812
	mov	__v3, __a4
	ldr	__ip, [__v3, #24]
	str	__a1, [__sp, #764]
	cmp	__ip, #2
	bne	|L..184|
	ldr	__ip, [__a1, #36]
	cmp	__ip, #1
	beq	|L..183|
|L..184|
	mov	__a1, __sp
	mov	__a2, __v3
	mov	__v2, #112
	mov	__a3, __v2
	bl	|memcpy|
	ldr	__v1, [__v3, #24]
	cmp	__v1, #0
	bne	|L..185|
	add	__a1, __sp, #480
	mov	__a2, __sp
	mov	__a3, __v2
	bl	|memcpy|
	add	__a3, __sp, __v2
	str	__a3, [__sp, #768]
	add	__a4, __sp, #204
	str	__a4, [__sp, #772]
	add	__ip, __sp, #296
	str	__ip, [__sp, #776]
	add	__a3, __sp, #388
	str	__a3, [__sp, #780]
	ldr	__a4, [__sp, #764]
	ldr	__ip, [__sp, #484]
	add	__a3, __sp, #612
	str	__a3, [__sp, #804]
	add	__a4, __a4, #66560
	str	__a4, [__sp, #808]
	add	__a4, __a4, #536
	str	__a4, [__sp, #808]
	str	__ip, [__sp, #784]
	mov	__v5, __v1
	ldr	__ip, |L..240|
|L..188|
	ldr	__a4, [__sp, #768]
	str	__ip, [__a4, __v5, asl #2]
	add	__v5, __v5, #1
	cmp	__v5, #22
	ble	|L..188|
	ldr	__ip, [__sp, #808]
	ldr	__a3, [__sp, #784]
	ldr	__v1, [__ip, #4]
	mov	__v5, #0
	cmp	__v1, __a3
	bge	|L..204|
|L..193|
	ldr	__a1, [__fp, #4]
	ldr	__ip, [__sp, #556]
	mov	__v1, __v1, asl #2
	ldr	__v6, |L..240|+4
	add	__a3, __sp, #748
	ldr	__a4, [__sp, #764]
	add	__a2, __a1, __v1
	str	__ip, [__sp, #748]
	mov	__lr, __pc
	ldr	__pc, [__a4, __v6]
	ldr	__a3, [__sp, #808]
	add	__ip, __v5, #2
	ldr	__a4, [__sp, #784]
	mov	__v2, #0
	ldr	__ip, [__a3, __ip, asl #2]
	add	__v4, __v5, #1
	str	__a1, [__sp, #788]
	cmp	__ip, __a4
	bge	|L..200|
|L..196|
	ldr	__a3, [__fp, #4]
	ldr	__a4, [__sp, #764]
	add	__a1, __a3, __v1
	add	__a2, __a3, __ip, asl #2
	ldr	__ip, [__sp, #748]
	add	__a3, __sp, #752
	str	__ip, [__sp, #752]
	mov	__lr, __pc
	ldr	__pc, [__a4, __v6]
	ldr	__a4, [__sp, #768]
	add	__a3, __v5, __v2
	ldr	__ip, [__a4, __a3, asl #2]
	ldr	__a4, [__sp, #752]
	cmp	__ip, __a4
	ble	|L..197|
	ldr	__ip, [__sp, #768]
	str	__a4, [__ip, __a3, asl #2]
	ldr	__a4, [__sp, #772]
	str	__v5, [__a4, __a3, asl #2]
	ldr	__a4, [__sp, #788]
	ldr	__ip, [__sp, #776]
	str	__a4, [__ip, __a3, asl #2]
	ldr	__ip, [__sp, #780]
	str	__a1, [__ip, __a3, asl #2]
|L..197|
	add	__v2, __v2, #1
	cmp	__v2, #7
	bgt	|L..200|
	ldr	__a3, [__sp, #808]
	add	__ip, __v5, __v2
	ldr	__a4, [__sp, #784]
	add	__ip, __ip, #2
	ldr	__ip, [__a3, __ip, asl #2]
	cmp	__ip, __a4
	blt	|L..196|
|L..200|
	mov	__v5, __v4
	cmp	__v4, #15
	bgt	|L..204|
	ldr	__a3, [__sp, #808]
	ldr	__a4, [__sp, #784]
	add	__ip, __v4, #1
	ldr	__v1, [__a3, __ip, asl #2]
	cmp	__v1, __a4
	blt	|L..193|
|L..204|
	mov	__a2, __sp
	ldr	__a1, [__sp, #804]
	mov	__a3, #112
	bl	|memcpy|
	ldr	__ip, [__sp, #808]
	ldr	__v4, [__sp, #616]
	mov	__v2, #2
	ldr	__a2, [__ip, __v2, asl #2]
	cmp	__a2, __v4
	bge	|L..185|
	ldr	__ip, [__sp, #112]
	ldr	__a3, [__sp, #700]
	ldr	__a4, [__v3, #0]
	add	__ip, __ip, __a3
	cmp	__a4, __ip
	str	__ip, [__sp, #756]
	ble	|L..185|
	mov	__v5, __v4, asl __v2
	ldr	__v6, |L..240|+4
|L..207|
	ldr	__a3, [__fp, #4]
	ldr	__a4, [__sp, #764]
	add	__a1, __a3, __a2, asl #2
	add	__a2, __a3, __v5
	add	__a3, __sp, #756
	mov	__lr, __pc
	ldr	__pc, [__a4, __v6]
	ldr	__a3, [__v3, #0]
	ldr	__ip, [__sp, #756]
	mov	__v1, __a1
	cmp	__a3, __ip
	ble	|L..209|
	mov	__a1, __v3
	add	__a2, __sp, #612
	mov	__a3, #112
	bl	|memcpy|
	str	__v1, [__v3, #40]
	ldr	__ip, [__sp, #756]
	mov	__a4, __v2, asl #2
	str	__ip, [__v3, #0]
	add	__ip, __a4, __sp
	add	__a3, __ip, #204
	ldr	__ip, [__a3, #-8]
	str	__ip, [__v3, #56]
	add	__ip, __ip, #2
	rsb	__ip, __ip, __v2
	str	__ip, [__v3, #60]
	add	__ip, __a4, __sp
	add	__a3, __ip, #296
	ldr	__ip, [__a3, #-8]
	add	__a4, __a4, __sp
	str	__ip, [__v3, #32]
	add	__a4, __a4, #388
	ldr	__ip, [__a4, #-8]
	str	__ip, [__v3, #36]
|L..209|
	add	__v2, __v2, #1
	cmp	__v2, #22
	bgt	|L..185|
	ldr	__a3, [__sp, #808]
	mov	__ip, __v2, asl #2
	ldr	__a2, [__a3, __ip]
	cmp	__a2, __v4
	bge	|L..185|
	add	__ip, __ip, __sp
	add	__ip, __ip, #112
	ldr	__a3, [__ip, #-8]
	ldr	__a4, [__sp, #700]
	ldr	__ip, [__v3, #0]
	add	__a3, __a3, __a4
	cmp	__ip, __a3
	str	__a3, [__sp, #756]
	bgt	|L..207|
|L..185|
	ldr	__v1, [__sp, #4]
	cmp	__v1, #0
	beq	|L..183|
	ldr	__a4, [__fp, #4]
	add	__ip, __a4, __v1, asl #2
	sub	__a4, __ip, #8
	ldmia	__a4, {__a3, __a4}
	orr	__a3, __a3, __a4
	cmp	__a3, #1
	bhi	|L..183|
	ldr	__ip, [__v3, #8]
	add	__v1, __ip, #2
	cmp	__v1, #576
	bgt	|L..183|
	mov	__a1, __sp
	mov	__a2, __v3
	mov	__a3, #112
	bl	|memcpy|
	mov	__v2, #0
	ldr	__lr, [__sp, #4]
	mov	__v4, __v2
	str	__v1, [__sp, #8]
	cmp	__v1, __lr
	ble	|L..218|
	mvn	__v6, #15
	mvn	__v5, #11
|L..220|
	ldr	__a3, [__fp, #4]
	add	__ip, __a3, __v1, asl #2
	ldr	__a1, [__ip, __v6]
	ldr	__a3, [__ip, __v5]
	ldr	__a4, [__ip, #-8]
	ldr	__a2, [__ip, #-4]
	ldr	__ip, |L..240|+8
	add	__a3, __a3, __a1, asl #1
	add	__a4, __a4, __a3, asl #1
	add	__a2, __a2, __a4, asl #1
	ldrb	__a1, [__ip, __a2]	; zero_extendqisi2
	sub	__v1, __v1, #4
	ldr	__ip, |L..240|+12
	cmp	__v1, __lr
	ldrb	__a3, [__ip, __a2]	; zero_extendqisi2
	add	__v2, __v2, __a1
	add	__v4, __v4, __a3
	bgt	|L..220|
|L..218|
	cmp	__v2, __v4
	str	__v1, [__sp, #4]
	mov	__ip, #0
	str	__ip, [__sp, #72]
	ble	|L..222|
	mov	__v2, __v4
	add	__ip, __ip, #1
	str	__ip, [__sp, #72]
|L..222|
	str	__v2, [__sp, #88]
	ldr	__a3, [__sp, #24]
	ldr	__ip, [__sp, #76]
	cmp	__a3, #0
	add	__ip, __v2, __ip
	str	__ip, [__sp, #0]
	bne	|L..223|
	add	__a1, __sp, #480
	mov	__a2, __sp
	mov	__a3, #112
	bl	|memcpy|
	ldr	__a4, [__sp, #764]
	mov	__v2, #2
	ldr	__v4, [__sp, #484]
	add	__ip, __a4, #66560
	add	__ip, __ip, #536
	ldr	__a2, [__ip, __v2, asl #2]
	add	__a3, __sp, #204
	str	__ip, [__sp, #808]
	add	__ip, __sp, #112
	str	__ip, [__sp, #792]
	add	__v6, __sp, #388
	str	__a3, [__sp, #796]
	add	__a4, __sp, #296
	str	__a4, [__sp, #800]
	cmp	__a2, __v4
	bge	|L..183|
	ldr	__ip, [__sp, #112]
	ldr	__a3, [__sp, #568]
	ldr	__a4, [__v3, #0]
	add	__ip, __ip, __a3
	cmp	__a4, __ip
	str	__ip, [__sp, #760]
	ble	|L..183|
	mov	__v5, __v4, asl __v2
|L..226|
	ldr	__ip, [__fp, #4]
	ldr	__a4, [__sp, #764]
	add	__a1, __ip, __a2, asl #2
	add	__a2, __ip, __v5
	ldr	__ip, |L..240|+4
	add	__a3, __sp, #760
	mov	__lr, __pc
	ldr	__pc, [__a4, __ip]
	ldr	__a3, [__v3, #0]
	ldr	__ip, [__sp, #760]
	mov	__v1, __a1
	cmp	__a3, __ip
	b	|L..239|
|L..241|
	ALIGN
|L..240|
	DCD	100000
	DCD	227008
	DCD	|t32l|
	DCD	|t33l|
|L..239|
	ble	|L..228|
	mov	__a1, __v3
	add	__a2, __sp, #480
	mov	__a3, #112
	bl	|memcpy|
	str	__v1, [__v3, #40]
	ldr	__ip, [__sp, #760]
	str	__ip, [__v3, #0]
	ldr	__ip, [__sp, #796]
	mov	__a4, __v2, asl #2
	add	__a3, __a4, __ip
	ldr	__ip, [__a3, #-8]
	str	__ip, [__v3, #56]
	add	__ip, __ip, #2
	rsb	__ip, __ip, __v2
	str	__ip, [__v3, #60]
	ldr	__ip, [__sp, #800]
	add	__a3, __a4, __ip
	ldr	__ip, [__a3, #-8]
	str	__ip, [__v3, #32]
	add	__a4, __a4, __v6
	ldr	__ip, [__a4, #-8]
	str	__ip, [__v3, #36]
|L..228|
	add	__v2, __v2, #1
	cmp	__v2, #22
	bgt	|L..183|
	ldr	__a3, [__sp, #808]
	mov	__ip, __v2, asl #2
	ldr	__a2, [__a3, __ip]
	cmp	__a2, __v4
	bge	|L..183|
	ldr	__a4, [__sp, #792]
	add	__ip, __ip, __a4
	ldr	__a3, [__ip, #-8]
	ldr	__a4, [__sp, #568]
	ldr	__ip, [__v3, #0]
	add	__a3, __a3, __a4
	cmp	__ip, __a3
	str	__a3, [__sp, #760]
	bgt	|L..226|
	ldmea	__fp, {__v1, __v2, __v3, __v4, __v5, __v6, __fp, __sp, __pc}
|L..223|
	ldr	__ip, |L..242|
	ldr	__a3, [__sp, #764]
	ldr	__v2, [__a3, __ip]
	cmp	__v2, __v1
	movge	__v2, __v1
	cmp	__v2, #0
	ble	|L..235|
	ldr	__a1, [__fp, #4]
	ldr	__ip, |L..242|+4
	mov	__a3, __sp
	ldr	__a4, [__sp, #764]
	add	__a2, __a1, __v2, asl #2
	mov	__lr, __pc
	ldr	__pc, [__a4, __ip]
	str	__a1, [__sp, #32]
|L..235|
	cmp	__v1, __v2
	ble	|L..236|
	ldr	__ip, [__fp, #4]
	ldr	__a4, [__sp, #764]
	add	__a1, __ip, __v2, asl #2
	add	__a2, __ip, __v1, asl #2
	ldr	__ip, |L..242|+4
	mov	__a3, __sp
	mov	__lr, __pc
	ldr	__pc, [__a4, __ip]
	str	__a1, [__sp, #36]
|L..236|
	ldr	__a3, [__v3, #0]
	ldr	__ip, [__sp, #0]
	cmp	__a3, __ip
	ble	|L..183|
	mov	__a1, __v3
	mov	__a2, __sp
	mov	__a3, #112
	bl	|memcpy|
|L..183|
	ldmea	__fp, {__v1, __v2, __v3, __v4, __v5, __v6, __fp, __sp, __pc}
|L..243|
	ALIGN
|L..242|
	DCD	67128
	DCD	227008
	ALIGN
|slen1_n|
	KEEP |slen1_n|
	DCD	1
	DCD	1
	DCD	1
	DCD	1
	DCD	8
	DCD	2
	DCD	2
	DCD	2
	DCD	4
	DCD	4
	DCD	4
	DCD	8
	DCD	8
	DCD	8
	DCD	16
	DCD	16
	ALIGN
|slen2_n|
	KEEP |slen2_n|
	DCD	1
	DCD	2
	DCD	4
	DCD	8
	DCD	1
	DCD	2
	DCD	4
	DCD	8
	DCD	2
	DCD	4
	DCD	8
	DCD	2
	DCD	4
	DCD	8
	DCD	4
	DCD	8
	ALIGN
|scfsi_band.37|
	KEEP |scfsi_band.37|
	DCD	0
	DCD	6
	DCD	11
	DCD	16
	DCD	21
	ALIGN
	EXPORT	|scfsi_calc|
|scfsi_calc|
	; args = 0, pretend = 0, frame = 24, alloca = 0
	; frame_needed = 0, anonymous_args = 0
	; nonlocal_label = 0, nonlocal_goto = 0
	stmfd	__sp!, {__v1, __v2, __v3, __v4, __v5, __v6, __lr}
	sub	__sp, __sp, #24
	mov	__v4, __a1
	rsb	__ip, __v4, __v4, asl #3
	mov	__ip, __ip, asl #4
	add	__ip, __ip, #272
	add	__ip, __a2, __ip
	mov	__lr, #0
	str	__a3, [__sp, #0]
	mov	__a4, __lr
	str	__ip, [__sp, #4]
	mov	__a3, __v4, asl #4
	str	__a3, [__sp, #16]
	add	__a2, __a2, #16
	str	__a2, [__sp, #20]
|L..248|
	add	__ip, __a3, __lr, asl #2
	add	__lr, __lr, #1
	cmp	__lr, #3
	str	__a4, [__a2, __ip]
	ble	|L..248|
	ldr	__a1, [__sp, #16]
	ldr	__a3, [__sp, #0]
	mov	__lr, #0
	ldr	__v6, |L..289|
	rsb	__ip, __v4, __a1
	add	__ip, __v4, __ip, asl #2
	mov	__v5, __ip, asl #2
	str	__a1, [__sp, #8]
	add	__a3, __v5, __a3
	str	__a3, [__sp, #12]
|L..253|
	mov	__a4, __lr, asl #2
	add	__a3, __lr, #1
	mov	__lr, __a3, asl #2
	ldr	__a2, [__v6, __a4]
	mov	__v2, __a4
	ldr	__ip, [__v6, __lr]
	mov	__v3, __a3
	cmp	__a2, __ip
	bge	|L..255|
	ldr	__a4, [__sp, #0]
	ldr	__ip, |L..289|
	add	__a1, __v5, __a4
	add	__v1, __a1, #488
	ldr	__lr, [__ip, __lr]
|L..257|
	mov	__ip, __a2, asl #2
	ldr	__a4, [__a1, __ip]
	ldr	__a3, [__v1, __ip]
	cmp	__a4, __a3
	bne	|L..255|
	add	__a2, __a2, #1
	cmp	__a2, __lr
	blt	|L..257|
|L..255|
	mov	__a4, __v3, asl #2
	ldr	__ip, [__v6, __a4]
	cmp	__a2, __ip
	bne	|L..252|
	ldr	__a1, |L..289|
	ldr	__a2, [__a1, __v2]
	cmp	__a2, __ip
	bge	|L..262|
	ldr	__ip, [__sp, #12]
	mvn	__lr, #0
	add	__a3, __ip, #488
	ldr	__ip, [__a1, __a4]
|L..264|
	str	__lr, [__a3, __a2, asl #2]
	add	__a2, __a2, #1
	cmp	__a2, __ip
	blt	|L..264|
|L..262|
	ldr	__a1, [__sp, #8]
	mov	__ip, #1
	ldr	__a4, [__sp, #20]
	add	__a3, __v2, __a1
	str	__ip, [__a4, __a3]
|L..252|
	mov	__lr, __v3
	cmp	__lr, #3
	bls	|L..253|
	mov	__v2, #0
	mov	__v5, __v2
	ldr	__a1, [__sp, #16]
	mov	__a2, __v2
	ldr	__a3, [__sp, #0]
	rsb	__ip, __v4, __a1
	add	__ip, __v4, __ip, asl #2
	add	__ip, __a3, __ip, asl #2
	add	__ip, __ip, #488
|L..270|
	ldr	__a3, [__ip, __a2, asl #2]
	cmp	__a3, #0
	blt	|L..269|
	add	__v2, __v2, #1
	cmp	__v5, __a3
	movlt	__v5, __a3
|L..269|
	add	__a2, __a2, #1
	cmp	__a2, #10
	ble	|L..270|
	mov	__v1, #0
	mov	__v3, __v1
	cmp	__a2, #20
	bgt	|L..275|
	ldr	__a4, [__sp, #16]
	ldr	__a1, [__sp, #0]
	rsb	__ip, __v4, __a4
	add	__ip, __v4, __ip, asl #2
	add	__ip, __a1, __ip, asl #2
	add	__a1, __ip, #488
|L..277|
	ldr	__a4, [__a1, __a2, asl #2]
	cmp	__a4, #0
	blt	|L..276|
	add	__v1, __v1, #1
	cmp	__v3, __a4
	movlt	__v3, __a4
|L..276|
	add	__a2, __a2, #1
	cmp	__a2, #20
	ble	|L..277|
|L..275|
	ldr	__v6, |L..289|+4
	ldr	__v4, |L..289|+8
	mov	__lr, #0
	ldr	__a1, |L..289|+12
|L..284|
	mov	__a3, __lr, asl #2
	ldr	__ip, [__v6, __a3]
	cmp	__v5, __ip
	bge	|L..283|
	ldr	__ip, [__v4, __a3]
	cmp	__v3, __ip
	bge	|L..283|
	ldr	__ip, |L..289|+16
	ldrb	__a3, [__ip, __lr]	; zero_extendqisi2
	ldrb	__a2, [__a1, __lr]	; zero_extendqisi2
	mul	__ip, __v1, __a3
	ldr	__a3, [__sp, #4]
	ldr	__a4, [__a3, #76]
	mla	__ip, __v2, __a2, __ip
	cmp	__a4, __ip
	strgt	__ip, [__a3, #76]
	strgt	__lr, [__a3, #16]
|L..283|
	add	__lr, __lr, #1
	cmp	__lr, #15
	b	|L..288|
|L..290|
	ALIGN
|L..289|
	DCD	|scfsi_band.37|
	DCD	|slen1_n|
	DCD	|slen2_n|
	DCD	|slen1_tab|
	DCD	|slen2_tab|
|L..288|
	ble	|L..284|
	add	__sp, __sp, #24
	ldmfd	__sp!, {__v1, __v2, __v3, __v4, __v5, __v6, __pc}
	ALIGN
	EXPORT	|best_scalefac_store|
|best_scalefac_store|
	; args = 8, pretend = 0, frame = 44, alloca = 0
	; frame_needed = 1, anonymous_args = 0
	; nonlocal_label = 0, nonlocal_goto = 0
	mov	__ip, __sp
	stmfd	__sp!, {__v1, __v2, __v3, __v4, __v5, __v6, __fp, __ip, __lr, __pc}
	sub	__fp, __ip, #4
	cmp	__sp, __sl
	bllt	|__rt_stkovf_split_small|
	sub	__sp, __sp, #44
	mov	__v3, __a2
	mov	__v4, __a3
	rsb	__ip, __v3, __v3, asl #3
	mov	__ip, __ip, asl #5
	add	__ip, __ip, #48
	ldr	__a2, [__fp, #4]
	rsb	__a3, __v4, __v4, asl #3
	add	__ip, __a2, __ip
	add	__a3, __ip, __a3, asl #4
	str	__a3, [__sp, #8]
	ldr	__a2, [__a3, #80]
	str	__a1, [__sp, #0]
	mov	__v1, #0
	str	__a4, [__sp, #4]
	cmp	__v1, __a2
	bge	|L..293|
	rsb	__a3, __v4, __v4, asl #4
	add	__a3, __v4, __a3, asl #2
	rsb	__ip, __v3, __v3, asl #4
	ldr	__a4, [__fp, #8]
	add	__ip, __v3, __ip, asl #2
	add	__ip, __a4, __ip, asl #3
	add	__v5, __ip, __a3, asl #2
	mov	__v6, __v5
|L..295|
	mov	__a3, __v1, asl #2
	add	__v2, __v1, #1
	ldr	__ip, [__v6, __a3]
	mov	__lr, __a3
	cmp	__ip, #0
	ble	|L..294|
	ldr	__a1, [__sp, #0]
	add	__ip, __a1, #66560
	add	__ip, __ip, #536
	ldr	__a1, [__ip, __v2, asl #2]
	ldr	__a2, [__ip, __lr]
	cmp	__a2, __a1
	bge	|L..298|
	add	__ip, __v4, __v4, asl #3
	ldr	__a4, [__sp, #4]
	add	__a3, __v3, __v3, asl #3
	add	__a3, __a4, __a3, asl #9
	add	__ip, __a3, __ip, asl #8
	ldr	__a4, [__ip, __a2, asl #2]
	cmp	__a4, #0
	bne	|L..298|
	mov	__a3, __ip
|L..299|
	add	__a2, __a2, #1
	cmp	__a2, __a1
	bge	|L..298|
	ldr	__ip, [__a3, __a2, asl #2]
	cmp	__ip, #0
	beq	|L..299|
|L..298|
	cmp	__a2, __a1
	moveq	__ip, #0
	streq	__ip, [__v5, __lr]
|L..294|
	ldr	__lr, [__sp, #8]
	ldr	__ip, [__lr, #80]
	mov	__v1, __v2
	cmp	__v1, __ip
	blt	|L..295|
|L..293|
	ldr	__a1, [__sp, #8]
	ldr	__a4, [__fp, #4]
	ldr	__v1, [__a1, #84]
	mov	__a2, #0
	str	__a2, [__sp, #12]
	mov	__a3, __v4, asl #4
	str	__a3, [__sp, #28]
	add	__a4, __a4, #16
	str	__a4, [__sp, #32]
	cmp	__v1, #11
	bgt	|L..306|
	ldr	__ip, [__sp, #0]
	ldr	__lr, [__fp, #8]
	add	__ip, __ip, #66560
	str	__ip, [__sp, #16]
	add	__ip, __ip, #628
	str	__ip, [__sp, #16]
	rsb	__ip, __v4, __a3
	add	__ip, __v4, __ip, asl #2
	rsb	__a3, __v3, __v3, asl #4
	add	__a3, __v3, __a3, asl #2
	add	__a3, __lr, __a3, asl #3
	add	__a3, __a3, __ip, asl #2
	add	__a3, __a3, #88
	add	__ip, __v4, __v4, asl #3
	str	__a3, [__sp, #20]
	mov	__ip, __ip, asl #8
	str	__ip, [__sp, #24]
|L..308|
	mov	__lr, #0
	add	__a3, __v1, #1
	mov	__v2, __a3
	ldr	__a1, [__sp, #16]
	add	__ip, __v1, __v1, asl #1
	ldr	__v5, [__a1, __v1, asl #2]
	mov	__v1, __ip, asl #2
	ldr	__a1, [__a1, __a3, asl #2]
|L..312|
	mov	__ip, __lr, asl #2
	add	__a3, __ip, __v1
	ldr	__a2, [__sp, #20]
	mov	__v6, __ip
	ldr	__a4, [__a2, __a3]
	rsb	__a3, __v5, __a1
	str	__a3, [__sp, #36]
	add	__lr, __lr, #1
	str	__lr, [__sp, #40]
	cmp	__a4, #0
	ble	|L..313|
	mov	__a2, __v5
	cmp	__a2, __a1
	bge	|L..315|
	ldr	__lr, [__sp, #4]
	add	__ip, __v3, __v3, asl #3
	add	__a4, __lr, __ip, asl #9
	ldr	__ip, [__sp, #24]
	ldr	__lr, [__sp, #12]
	add	__a3, __ip, __a4
	ldr	__ip, [__a3, __lr, asl #2]
	add	__a3, __lr, #1
	cmp	__ip, #0
	mov	__ip, __v4, asl #3
	bne	|L..315|
	add	__ip, __ip, __v4
	add	__a4, __a4, __ip, asl #8
|L..316|
	add	__a2, __a2, #1
	cmp	__a2, __a1
	bge	|L..315|
	ldr	__ip, [__a4, __a3, asl #2]
	add	__a3, __a3, #1
	cmp	__ip, #0
	beq	|L..316|
|L..315|
	cmp	__a2, __a1
	bne	|L..313|
	add	__a3, __v6, __v1
	ldr	__a2, [__sp, #20]
	mov	__ip, #0
	str	__ip, [__a2, __a3]
|L..313|
	ldr	__a3, [__sp, #12]
	ldr	__a4, [__sp, #36]
	ldr	__lr, [__sp, #40]
	add	__a3, __a3, __a4
	cmp	__lr, #2
	str	__a3, [__sp, #12]
	ble	|L..312|
	mov	__v1, __v2
	cmp	__v1, #11
	ble	|L..308|
|L..306|
	ldr	__lr, [__sp, #8]
	ldr	__ip, [__lr, #0]
	ldr	__a3, [__lr, #68]
	ldr	__a4, [__lr, #76]
	cmp	__a3, #0
	rsb	__ip, __a4, __ip
	str	__ip, [__lr, #0]
	bne	|L..323|
	ldr	__a3, [__lr, #64]
	cmp	__a3, #0
	bne	|L..323|
	mov	__v1, __a3
	ldr	__a4, [__lr, #80]
	mov	__lr, __v1
	ldr	__a1, [__sp, #8]
	cmp	__v1, __a4
	mov	__v5, __a4
	ldr	__a2, [__a1, #84]
	bge	|L..325|
	ldr	__ip, [__sp, #28]
	ldr	__a1, [__fp, #8]
	rsb	__a3, __v4, __ip
	add	__a3, __v4, __a3, asl #2
	rsb	__ip, __v3, __v3, asl #4
	add	__ip, __v3, __ip, asl #2
	add	__ip, __a1, __ip, asl #3
	add	__a3, __ip, __a3, asl #2
|L..327|
	ldr	__ip, [__a3, __v1, asl #2]
	add	__v1, __v1, #1
	cmp	__v1, __a4
	orr	__lr, __lr, __ip
	blt	|L..327|
|L..325|
	mov	__v1, __a2
	cmp	__v1, #11
	bgt	|L..330|
	rsb	__ip, __v3, __v3, asl #4
	ldr	__a2, [__sp, #28]
	add	__ip, __v3, __ip, asl #2
	ldr	__a4, [__fp, #8]
	rsb	__a3, __v4, __a2
	add	__a3, __v4, __a3, asl #2
	add	__ip, __a4, __ip, asl #3
	add	__ip, __ip, __a3, asl #2
	add	__a1, __ip, #88
|L..332|
	mov	__a4, #0
	add	__v2, __v1, #1
	add	__ip, __v1, __v1, asl #1
	mov	__a2, __ip, asl #2
|L..336|
	add	__ip, __a2, __a4, asl #2
	add	__a4, __a4, #1
	ldr	__a3, [__a1, __ip]
	cmp	__a4, #2
	orr	__lr, __lr, __a3
	ble	|L..336|
	mov	__v1, __v2
	cmp	__v1, #11
	ble	|L..332|
|L..330|
	eor	__ip, __lr, #1
	cmp	__lr, #0
	andne	__ip, __ip, #1
	moveq	__ip, #0
	cmp	__ip, #0
	beq	|L..323|
	mov	__v1, #0
	cmp	__v1, __v5
	mov	__lr, __v3, asl #4
	bge	|L..341|
	ldr	__ip, [__sp, #28]
	ldr	__a1, [__fp, #8]
	rsb	__a3, __v4, __ip
	add	__a3, __v4, __a3, asl #2
	rsb	__ip, __v3, __lr
	add	__ip, __v3, __ip, asl #2
	add	__ip, __a1, __ip, asl #3
	add	__a2, __ip, __a3, asl #2
|L..343|
	mov	__ip, __v1, asl #2
	ldr	__a3, [__a2, __ip]
	add	__a3, __a3, __a3, lsr #31
	mov	__a3, __a3, asr #1
	str	__a3, [__a2, __ip]
	ldr	__a3, [__sp, #8]
	ldr	__a4, [__a3, #80]
	add	__v1, __v1, #1
	cmp	__v1, __a4
	blt	|L..343|
|L..341|
	ldr	__a4, [__sp, #8]
	ldr	__v1, [__a4, #84]
	cmp	__v1, #11
	bgt	|L..346|
	ldr	__ip, [__sp, #28]
	ldr	__a1, [__fp, #8]
	rsb	__a3, __v4, __ip
	add	__a3, __v4, __a3, asl #2
	rsb	__ip, __v3, __lr
	add	__ip, __v3, __ip, asl #2
	add	__ip, __a1, __ip, asl #3
	add	__ip, __ip, __a3, asl #2
	add	__a1, __ip, #88
|L..348|
	mov	__a4, #0
	add	__v2, __v1, #1
	add	__ip, __v1, __v1, asl #1
	mov	__a2, __ip, asl #2
|L..352|
	add	__a3, __a2, __a4, asl #2
	add	__a4, __a4, #1
	ldr	__ip, [__a1, __a3]
	cmp	__a4, #2
	add	__ip, __ip, __ip, lsr #31
	mov	__ip, __ip, asr #1
	str	__ip, [__a1, __a3]
	ble	|L..352|
	mov	__v1, __v2
	cmp	__v1, #11
	ble	|L..348|
|L..346|
	ldr	__a2, [__sp, #8]
	mov	__ip, #1
	str	__ip, [__a2, #68]
	ldr	__a4, [__sp, #0]
	ldr	__ip, |L..363|
	ldr	__a3, [__a4, #36]
	str	__ip, [__a2, #76]
	cmp	__a3, #2
	bne	|L..355|
	rsb	__ip, __v3, __lr
	ldr	__lr, [__fp, #8]
	add	__ip, __v3, __ip, asl #2
	ldr	__a2, [__sp, #28]
	add	__ip, __lr, __ip, asl #3
	rsb	__a1, __v4, __a2
	add	__a1, __v4, __a1, asl #2
	ldr	__a2, [__sp, #8]
	add	__a1, __ip, __a1, asl #2
	bl	|scale_bitcount|
	b	|L..323|
|L..355|
	ldr	__a1, [__sp, #0]
	rsb	__ip, __v3, __lr
	ldr	__a3, [__fp, #8]
	add	__ip, __v3, __ip, asl #2
	ldr	__a4, [__sp, #28]
	add	__ip, __a3, __ip, asl #3
	rsb	__a2, __v4, __a4
	add	__a2, __v4, __a2, asl #2
	ldr	__a3, [__sp, #8]
	add	__a2, __ip, __a2, asl #2
	bl	|scale_bitcount_lsf|
|L..323|
	mov	__lr, #0
	ldr	__a1, [__sp, #28]
	mov	__a3, __lr
	ldr	__a4, [__sp, #32]
|L..360|
	add	__ip, __a1, __lr, asl #2
	add	__lr, __lr, #1
	cmp	__lr, #3
	str	__a3, [__a4, __ip]
	ble	|L..360|
	ldr	__lr, [__sp, #0]
	ldr	__ip, [__lr, #36]
	cmp	__ip, #2
	cmpeq	__v3, #1
	bne	|L..362|
	rsb	__ip, __v4, __v4, asl #3
	ldr	__a1, [__fp, #4]
	mov	__a4, __ip, asl #4
	add	__a3, __a1, #72
	ldr	__ip, [__a3, __a4]
	cmp	__ip, #2
	beq	|L..362|
	add	__ip, __a1, #296
	ldr	__a3, [__ip, __a4]
	cmp	__a3, #2
	beq	|L..362|
	ldmib	__fp, {__a2, __a3}	; phole ldm
	mov	__a1, __v4
	bl	|scfsi_calc|
|L..362|
	ldr	__a2, [__sp, #8]
	ldr	__ip, [__a2, #0]
	ldr	__a3, [__a2, #76]
	add	__ip, __ip, __a3
	str	__ip, [__a2, #0]
	ldmea	__fp, {__v1, __v2, __v3, __v4, __v5, __v6, __fp, __sp, __pc}
|L..364|
	ALIGN
|L..363|
	DCD	99999999
	ALIGN
|scale_short|
	KEEP |scale_short|
	DCD	0
	DCD	18
	DCD	36
	DCD	54
	DCD	54
	DCD	36
	DCD	54
	DCD	72
	DCD	54
	DCD	72
	DCD	90
	DCD	72
	DCD	90
	DCD	108
	DCD	108
	DCD	126
	ALIGN
|scale_mixed|
	KEEP |scale_mixed|
	DCD	0
	DCD	18
	DCD	36
	DCD	54
	DCD	51
	DCD	35
	DCD	53
	DCD	71
	DCD	52
	DCD	70
	DCD	88
	DCD	69
	DCD	87
	DCD	105
	DCD	104
	DCD	122
	ALIGN
|scale_long|
	KEEP |scale_long|
	DCD	0
	DCD	10
	DCD	20
	DCD	30
	DCD	33
	DCD	21
	DCD	31
	DCD	41
	DCD	32
	DCD	42
	DCD	52
	DCD	43
	DCD	53
	DCD	63
	DCD	64
	DCD	74
	ALIGN
	EXPORT	|scale_bitcount|
|scale_bitcount|
	; args = 0, pretend = 0, frame = 8, alloca = 0
	; frame_needed = 0, anonymous_args = 0
	; nonlocal_label = 0, nonlocal_goto = 0
	stmfd	__sp!, {__v1, __v2, __v3, __v4, __v5, __v6, __lr}
	sub	__sp, __sp, #8
	mov	__v4, #0
	mov	__v3, __v4
	mov	__v1, __a2
	ldr	__ip, [__v1, #24]
	mov	__a3, #2
	str	__a3, [__sp, #0]
	cmp	__ip, __a3
	bne	|L..366|
	ldr	__ip, [__v1, #28]
	ldr	__lr, |L..423|
	add	__v5, __a1, #88
	str	__lr, [__sp, #4]
	cmp	__ip, __v4
	ldr	__v6, [__v1, #84]
	beq	|L..367|
	ldr	__ip, [__v1, #80]
	mov	__lr, __v4
	ldr	__a3, |L..423|+4
	cmp	__v4, __ip
	str	__a3, [__sp, #4]
	bge	|L..367|
	mov	__a3, __ip
|L..371|
	ldr	__ip, [__a1, __lr, asl #2]
	add	__lr, __lr, #1
	cmp	__v3, __ip
	movlt	__v3, __ip
	cmp	__lr, __a3
	blt	|L..371|
|L..367|
	mov	__ip, #0
|L..377|
	mov	__lr, __v6
	cmp	__lr, #5
	mov	__a2, __ip, asl #2
	add	__v2, __ip, #1
	bgt	|L..379|
	mov	__a1, __a2
	mov	__a4, __v5
|L..381|
	add	__ip, __lr, __lr, asl #1
	add	__ip, __a1, __ip, asl #2
	ldr	__a3, [__a4, __ip]
	add	__lr, __lr, #1
	cmp	__v3, __a3
	movlt	__v3, __a3
	cmp	__lr, #5
	ble	|L..381|
|L..379|
	mov	__lr, #6
	mov	__a1, __a2
	mov	__a4, __v5
|L..387|
	add	__ip, __lr, __lr, asl #1
	add	__ip, __a1, __ip, asl #2
	ldr	__a3, [__a4, __ip]
	add	__lr, __lr, #1
	cmp	__v4, __a3
	movlt	__v4, __a3
	cmp	__lr, #11
	ble	|L..387|
	mov	__ip, __v2
	cmp	__ip, #2
	ble	|L..377|
	b	|L..391|
|L..424|
	ALIGN
|L..423|
	DCD	|scale_short|
	DCD	|scale_mixed|
|L..366|
	ldr	__ip, |L..426|
	str	__ip, [__sp, #4]
	mov	__lr, __v4
	ldr	__a3, [__v1, #64]
|L..395|
	ldr	__ip, [__a1, __lr, asl #2]
	add	__lr, __lr, #1
	cmp	__ip, __v3
	movge	__v3, __ip
	cmp	__lr, #10
	ble	|L..395|
	cmp	__a3, #0
	bne	|L..398|
	ldr	__a4, |L..426|+4
	mov	__lr, #11
	ldr	__ip, [__a1, __lr, asl #2]
	ldrb	__a3, [__a4, __lr]	; zero_extendqisi2
	cmp	__ip, __a3
	blt	|L..400|
|L..401|
	add	__lr, __lr, #1
	cmp	__lr, #20
	bgt	|L..400|
	ldrb	__a3, [__a4, __lr]	; zero_extendqisi2
	ldr	__ip, [__a1, __lr, asl #2]
	cmp	__ip, __a3
	bge	|L..401|
|L..400|
	cmp	__lr, #21
	bne	|L..398|
	mov	__ip, #1
	str	__ip, [__v1, #64]
	mov	__lr, #11
	ldr	__a2, |L..426|+4
|L..409|
	mov	__ip, __lr, asl #2
	ldrb	__a4, [__a2, __lr]	; zero_extendqisi2
	add	__lr, __lr, #1
	ldr	__a3, [__a1, __ip]
	cmp	__lr, #20
	rsb	__a3, __a4, __a3
	str	__a3, [__a1, __ip]
	ble	|L..409|
|L..398|
	mov	__lr, #11
|L..414|
	ldr	__ip, [__a1, __lr, asl #2]
	add	__lr, __lr, #1
	cmp	__ip, __v4
	movge	__v4, __ip
	cmp	__lr, #20
	ble	|L..414|
|L..391|
	ldr	__a1, |L..426|+8
	ldr	__a2, |L..426|+12
	ldr	__ip, |L..426|+16
	mov	__a4, #0
	str	__ip, [__v1, #76]
|L..420|
	mov	__a3, __a4, asl #2
	ldr	__ip, [__a1, __a3]
	cmp	__v3, __ip
	bge	|L..419|
	ldr	__ip, [__a2, __a3]
	cmp	__v4, __ip
	bge	|L..419|
	ldr	__lr, [__sp, #4]
	ldr	__ip, [__v1, #76]
	ldr	__a3, [__lr, __a4, asl #2]
	cmp	__ip, __a3
	ble	|L..419|
	str	__a3, [__v1, #76]
	mov	__a3, #0
	str	__a3, [__sp, #0]
	str	__a4, [__v1, #16]
|L..419|
	add	__a4, __a4, #1
	cmp	__a4, #15
	ble	|L..420|
	ldr	__a1, [__sp, #0]
	b	|L..425|
|L..427|
	ALIGN
|L..426|
	DCD	|scale_long|
	DCD	|pretab|
	DCD	|slen1_n|
	DCD	|slen2_n|
	DCD	100000
|L..425|
	add	__sp, __sp, #8
	ldmfd	__sp!, {__v1, __v2, __v3, __v4, __v5, __v6, __pc}
	ALIGN
|max_range_sfac_tab|
	KEEP |max_range_sfac_tab|
	DCD	15
	DCD	15
	DCD	7
	DCD	7
	DCD	15
	DCD	15
	DCD	7
	DCD	0
	DCD	7
	DCD	3
	DCD	0
	DCD	0
	DCD	15
	DCD	31
	DCD	31
	DCD	0
	DCD	7
	DCD	7
	DCD	7
	DCD	0
	DCD	3
	DCD	3
	DCD	0
	DCD	0
	ALIGN
|log2tab.47|
	KEEP |log2tab.47|
	DCD	0
	DCD	1
	DCD	2
	DCD	2
	DCD	3
	DCD	3
	DCD	3
	DCD	3
	DCD	4
	DCD	4
	DCD	4
	DCD	4
	DCD	4
	DCD	4
	DCD	4
	DCD	4
	ALIGN
|LC..0|
	DCB &69, &6e, &74, &65
	DCB &6e, &73, &69, &74
	DCB &79, &20, &73, &74
	DCB &65, &72, &65, &6f
	DCB &20, &6e, &6f, &74
	DCB &20, &69, &6d, &70
	DCB &6c, &65, &6d, &65
	DCB &6e, &74, &65, &64
	DCB &20, &79, &65, &74
	DCB &0a, &00
	ALIGN
	EXPORT	|scale_bitcount_lsf|
|scale_bitcount_lsf|
	; args = 0, pretend = 0, frame = 44, alloca = 0
	; frame_needed = 1, anonymous_args = 0
	; nonlocal_label = 0, nonlocal_goto = 0
	mov	__ip, __sp
	stmfd	__sp!, {__v1, __v2, __v3, __v4, __v5, __v6, __fp, __ip, __lr, __pc}
	sub	__fp, __ip, #4
	cmp	__sp, __sl
	bllt	|__rt_stkovf_split_small|
	sub	__sp, __sp, #44
	str	__a1, [__sp, #16]
	mov	__lr, #0
	str	__a2, [__sp, #20]
	mov	__v6, __a3
	ldr	__ip, [__v6, #64]
	mov	__a3, __lr
	cmp	__ip, __lr
	movne	__ip, #2
	moveq	__ip, __lr
	str	__ip, [__sp, #24]
|L..434|
	mov	__ip, __lr, asl #2
	add	__lr, __lr, #1
	cmp	__lr, #3
	str	__a3, [__sp, __ip]
	ble	|L..434|
	ldr	__ip, [__v6, #24]
	cmp	__ip, #2
	bne	|L..436|
	mov	__a1, #1
	str	__a1, [__sp, #28]
	ldr	__a2, [__sp, #24]
	ldr	__a4, |L..490|
	cmp	__a2, #0
	movne	__a3, #96
	moveq	__a3, #0
	add	__ip, __a4, __a1, asl #4
	add	__a3, __a3, __ip
	sub	__a1, __a1, #1
	mov	__v2, __a1
	str	__a3, [__sp, #32]
	mov	__ip, __a2, asl #1
	str	__ip, [__sp, #36]
	mov	__a2, __a2, asl #4
	str	__a2, [__sp, #40]
|L..440|
	ldr	__a3, [__sp, #32]
	ldr	__a4, [__a3, __a1, asl #2]
	ldr	__a3, |L..490|+4
	mov	__lr, #0
	smull	__a2, __ip, __a3, __a4
	sub	__v1, __ip, __a4, asr #31
	cmp	__lr, __v1
	bge	|L..439|
	ldr	__a3, [__sp, #20]
	mov	__a2, __a1, asl #2
	add	__v5, __a3, #88
|L..444|
	mov	__a4, #0
	add	__v3, __lr, #1
	add	__v4, __v2, #1
	add	__ip, __v2, __v2, asl #1
	mov	__lr, __ip, asl #2
|L..448|
	add	__ip, __lr, __a4, asl #2
	ldr	__ip, [__v5, __ip]
	ldr	__a3, [__sp, __a2]
	cmp	__ip, __a3
	strgt	__ip, [__sp, __a2]
|L..447|
	add	__a4, __a4, #1
	cmp	__a4, #2
	ble	|L..448|
	mov	__lr, __v3
	mov	__v2, __v4
	cmp	__lr, __v1
	blt	|L..444|
|L..439|
	add	__a1, __a1, #1
	cmp	__a1, #3
	ble	|L..440|
	b	|L..453|
|L..436|
	mov	__a4, #0
	str	__a4, [__sp, #28]
	ldr	__a1, [__sp, #24]
	ldr	__a2, |L..490|
	mov	__v2, __a4
	ldr	__a3, [__sp, #24]
	cmp	__a1, __a4
	movne	__ip, #96
	moveq	__ip, __a4
	add	__ip, __ip, __a2
	str	__ip, [__sp, #32]
	mov	__a1, __a4
	ldr	__a4, [__sp, #24]
	mov	__a3, __a3, asl #1
	str	__a3, [__sp, #36]
	mov	__a4, __a4, asl #4
	str	__a4, [__sp, #40]
|L..457|
	ldr	__ip, [__sp, #32]
	ldr	__v1, [__ip, __a1, asl #2]
	mov	__lr, #0
	cmp	__lr, __v1
	bge	|L..456|
	mov	__a4, __a1, asl #2
|L..461|
	ldr	__a2, [__sp, #20]
	ldr	__ip, [__sp, __a4]
	ldr	__a3, [__a2, __v2, asl #2]
	cmp	__a3, __ip
	strgt	__a3, [__sp, __a4]
|L..460|
	add	__lr, __lr, #1
	add	__v2, __v2, #1
	cmp	__lr, __v1
	blt	|L..461|
|L..456|
	add	__a1, __a1, #1
	cmp	__a1, #3
	ble	|L..457|
|L..453|
	mov	__v2, #0
	ldr	__a2, [__sp, #40]
	mov	__a1, __v2
	ldr	__lr, |L..490|+8
|L..468|
	mov	__ip, __a1, asl #2
	ldr	__a4, [__sp, __ip]
	add	__ip, __ip, __a2
	ldr	__a3, [__lr, __ip]
	add	__a1, __a1, #1
	cmp	__a4, __a3
	addgt	__v2, __v2, #1
	cmp	__a1, #3
	ble	|L..468|
	cmp	__v2, #0
	bne	|L..471|
	ldr	__a4, [__sp, #36]
	ldr	__ip, [__sp, #24]
	ldr	__a2, |L..490|
	add	__a3, __a4, __ip
	ldr	__a4, [__sp, #28]
	mov	__a1, __v2
	ldr	__lr, |L..490|+12
	add	__ip, __a2, __a4, asl #4
	add	__ip, __ip, __a3, asl #4
	add	__a2, __v6, #96
	str	__ip, [__v6, #92]
|L..475|
	mov	__ip, __a1, asl #2
	ldr	__a3, [__sp, __ip]
	add	__a1, __a1, #1
	ldr	__a4, [__lr, __a3, asl #2]
	cmp	__a1, #3
	str	__a4, [__a2, __ip]
	ble	|L..475|
	add	__a3, __v6, #96
	ldmia	__a3, {__a3, __a4, __ip}	; phole ldm
	ldr	__a1, [__sp, #24]
	ldr	__a2, [__v6, #108]
	cmp	__a1, #1
	beq	|L..479|
	bgt	|L..483|
	cmp	__a1, #0
	beq	|L..478|
	b	|L..481|
|L..483|
	ldr	__a2, [__sp, #24]
	cmp	__a2, #2
	beq	|L..480|
	b	|L..481|
|L..478|
	add	__a3, __a3, __a3, asl #2
	add	__a3, __a3, __a4
	mov	__ip, __ip, asl #2
	add	__ip, __ip, __a3, asl #4
	add	__ip, __ip, __a2
	str	__ip, [__v6, #16]
	b	|L..471|
|L..479|
	add	__a3, __a3, __a3, asl #2
	add	__a3, __a3, __a4
	add	__ip, __ip, #400
	add	__ip, __ip, __a3, asl #2
	str	__ip, [__v6, #16]
	b	|L..471|
|L..480|
	add	__ip, __a3, __a3, asl #1
	add	__a3, __a4, #500
	add	__ip, __ip, __a3
	str	__ip, [__v6, #16]
	b	|L..471|
|L..481|
	ldr	__a2, |L..490|+16
	ldr	__a1, [__sp, #16]
	bl	|lame_errorf|
|L..471|
	cmp	__v2, #0
	bne	|L..484|
	mov	__a1, __v2
	str	__v2, [__v6, #76]
	add	__v1, __v6, #96
	ldr	__lr, [__v6, #92]
|L..488|
	ldr	__a2, [__v1, __a1, asl #2]
	ldr	__a4, [__lr, __a1, asl #2]
	add	__a1, __a1, #1
	ldr	__a3, [__v6, #76]
	cmp	__a1, #3
	mla	__ip, __a4, __a2, __a3
	str	__ip, [__v6, #76]
	ble	|L..488|
|L..484|
	mov	__a1, __v2
	ldmea	__fp, {__v1, __v2, __v3, __v4, __v5, __v6, __fp, __sp, __pc}
|L..491|
	ALIGN
|L..490|
	DCD	|nr_of_sfb_block|
	DCD	1431655766
	DCD	|max_range_sfac_tab|
	DCD	|log2tab.47|
	DCD	|LC..0|
	ALIGN
	EXPORT	|huffman_init|
|huffman_init|
	; args = 0, pretend = 0, frame = 0, alloca = 0
	; frame_needed = 0, anonymous_args = 0
	; nonlocal_label = 0, nonlocal_goto = 0
	stmfd	__sp!, {__v1, __v2, __v3, __v4, __v5, __v6, __lr}
	mov	__v1, #2
	mov	__v3, __a1
	add	__v2, __v3, #66560
	add	__v2, __v2, #536
	ldr	__a3, |L..511|
	add	__v4, __v3, #32512
	ldr	__ip, |L..511|+4
	add	__v4, __v4, #156
	str	__ip, [__v3, __a3]
|L..496|
	mov	__a3, #0
	sub	__lr, __v1, #2
	sub	__v6, __v1, #1
	add	__v5, __v1, #2
|L..499|
	add	__a3, __a3, #1
	ldr	__ip, [__v2, __a3, asl #2]
	cmp	__ip, __v1
	blt	|L..499|
	mov	__ip, __a3, asl #3
	ldr	__a3, |L..511|+8
	ldr	__a2, [__a3, __ip]
	add	__a3, __a2, #1
	ldr	__a4, [__v2, __a3, asl #2]
	mov	__a1, __ip
	cmp	__a4, __v1
	ble	|L..501|
	add	__a4, __v3, #66560
	add	__a4, __a4, #536
|L..502|
	sub	__a2, __a2, #1
	add	__ip, __a2, #1
	ldr	__a3, [__a4, __ip, asl #2]
	cmp	__a3, __v1
	bgt	|L..502|
|L..501|
	cmp	__a2, #0
	ldrlt	__ip, |L..511|+8
	ldrlt	__a2, [__ip, __a1]
|L..504|
	ldr	__a3, |L..511|+12
	strb	__a2, [__v4, __lr]
	ldr	__a2, [__a3, __a1]
	ldrb	__ip, [__v4, __lr]	; zero_extendqisi2
	add	__ip, __a2, __ip
	add	__ip, __ip, #2
	ldr	__a3, [__v2, __ip, asl #2]
	cmp	__a3, __v1
	ble	|L..506|
	add	__ip, __v3, #32512
	add	__ip, __ip, #156
	add	__a4, __v3, #66560
	add	__a4, __a4, #536
	ldrb	__lr, [__ip, __lr]	; zero_extendqisi2
|L..507|
	sub	__a2, __a2, #1
	add	__ip, __a2, __lr
	add	__ip, __ip, #2
	ldr	__a3, [__a4, __ip, asl #2]
	cmp	__a3, __v1
	bgt	|L..507|
|L..506|
	cmp	__a2, #0
	ldrlt	__ip, |L..511|+12
	ldrlt	__a2, [__ip, __a1]
|L..509|
	mov	__v1, __v5
	cmp	__v1, #576
	strb	__a2, [__v4, __v6]
	ble	|L..496|
	ldmfd	__sp!, {__v1, __v2, __v3, __v4, __v5, __v6, __pc}
|L..512|
	ALIGN
|L..511|
	DCD	227008
	DCD	|choose_table_nonMMX|
	DCD	|subdv_table|
	DCD	|subdv_table|+4


 EXPORT |count_bits|
|count_bits|
  stmfd r13!, {r4 - r9, r14}
 cmp r13, r10
 bllt |__rt_stkovf_split_small|
  mov r6, r0
  mov r4, r3
  ldr r3, [r3, #12]
  mov r5, r1
  ldr r7, |L..1108n|
  mov r9, r2
  add r7, r7, r3, lsl #3
  mov r12, r2

  stmfd r13!, {r4 - r6, r10}
 ldmia r7, {r0, r2}
 bl |mech_ldfd|         ; ldfd f1, [r7]
 adr r7, |L..1108n|+4
 ldmia r7, {r3 - r5}    ; ldfe f0, |L..1108n|+4
 bl |mech_rdfd|         ; rdfd f1, f1, f0
 orr r0, r0, r3
 eor r3, r0, #1<<31
 mov r4, r1
 mov r5, r2
 mov r10, #0

|L..297n|
 ldmia r12, {r0, r2}
 bl |mech_ldfd|         ; ldfd f0, [r12]
 bl do_cnf              ; cmf f0, f1
 msr cpsr_flg, r6
  bgt |L..1089n|
  add r12, r12, #8
  add r10, r10, #1
  cmp r10, #576
  blt |L..297n|

 ldmfd r13!, {r4 - r6, r10}

 mov r0, r9
 ldr r12, |L..1108n|+16
 mov r1, r5
 ldr r12, [r6, r12]
 mov r2, r4
  ldr r7, |L..1108n|
 cmp r12, #0
 ldr r12, [r4, #12]
 add r12, r7, r12, lsl #3
 ldmia r12, {r2-r3} ; double
 adrne r14, |L..154n|
 bne |quantize_xrpow|
 bleq |quantize_xrpow_ISO|
|L..154n|
 mov r0, r6
 mov r1, r5
 mov r2, r4
 ldmfd r13!, {r4 - r9, r14}
 b |count_bits_long|

|L..1089n|
 add r13, r13, #3*4 ; r4 - r6
 ldmfd r13!, {r10}
 ldr r0, |L..1108n|+20
 ldmfd r13!, {r4 - r9, r15}

|L..1108n|
 DCD |ipow20|
 dcd &400C, &80380000, 0    ; long double 8206
 DCD 32044
 DCD 100000


	EXPORT	|ix_max|
|ix_max|
	; args = 0, pretend = 0, frame = 0, alloca = 0
	; frame_needed = 0, anonymous_args = 0
	; nonlocal_label = 0, nonlocal_goto = 0
	stmfd	__sp!, {__lr}
	mov	__a4, #0
	mov	__lr, __a4
|L..8|
	ldr	__a3, [__a1], #4
	ldr	__ip, [__a1], #4
	cmp	__a4, __a3
	movlt	__a4, __a3
	cmp	__lr, __ip
	movlt	__lr, __ip
	cmp	__a1, __a2
	bcc	|L..8|
	cmp	__a4, __lr
	movge	__a1, __a4
	movlt	__a1, __lr
	ldmfd	__sp!, {__pc}
	ALIGN
	EXPORT	|count_bit_ESC|
|count_bit_ESC|
	; args = 4, pretend = 0, frame = 0, alloca = 0
	; frame_needed = 0, anonymous_args = 0
	; nonlocal_label = 0, nonlocal_goto = 0
	stmfd	__sp!, {__v1, __v2, __v3, __v4, __lr}
	ldr	__v4, [__sp, #20]
	mov	__v2, __a2
	ldr	__ip, |L..517|
	mov	__v1, __a3
	ldr	__a2, [__ip, __v1, asl #4]
	ldr	__a3, [__ip, __a4, asl #4]
	mov	__lr, #0
	ldr	__v3, |L..517|+4
	add	__a2, __a3, __a2, asl #16
|L..18|
	ldr	__ip, [__a1], #4
	cmp	__ip, #0
	ldr	__a3, [__a1], #4
	beq	|L..14|
	cmp	__ip, #14
	movgt	__ip, #15
	addgt	__lr, __lr, __a2
|L..15|
	mov	__ip, __ip, asl #4
|L..14|
	cmp	__a3, #0
	beq	|L..16|
	cmp	__a3, #14
	movgt	__a3, #15
	addgt	__lr, __lr, __a2
|L..17|
	add	__ip, __ip, __a3
|L..16|
	ldr	__ip, [__v3, __ip, asl #2]
	cmp	__a1, __v2
	add	__lr, __lr, __ip
	bcc	|L..18|
	ldr	__ip, |L..517|+8
	and	__ip, __lr, __ip
	mov	__lr, __lr, asr #16
	cmp	__lr, __ip
	movgt	__lr, __ip
	movgt	__v1, __a4
|L..19|
	ldr	__ip, [__v4, #0]
	mov	__a1, __v1
	add	__ip, __ip, __lr
	str	__ip, [__v4, #0]
	ldmfd	__sp!, {__v1, __v2, __v3, __v4, __pc}
|L..518|
	ALIGN
|L..517|
	DCD	|ht|
	DCD	|largetbl|
	DCD	65535
	END
